Developments in semiconductor technologies over the last few years have allowed the Figure of Merit (FoM) and circuit efficiency to be maintained, or even in some cases improved, as the size of a semiconductor device continually shrinks. Exemplary semiconductor technologies that use a shrinking form factor include embedded die and packaging technologies. In one example, an integrated circuit (IC) chip die may be located within a core layer of a printed circuit board (PCB), or between layers of a multi-layer circuit board. This technique frees up surface area on the PCB layer surfaces for other circuit components. In some cases, multiple chip dice may be located within different layers or sets of layers of a multi-layer PCB.
Interlayer connections between embedded components are sometimes managed using vias drilled through one or more of the layers of the PCB, and plated with a conductive material. The vias may be global vias, extending through all layers of the PCB, or they may be blind vias, extending through one or more layers, but not fully through all layers of the PCB. Conductive tracks formed on one or more PCB layers may be electrically coupled to one or more of the vias, providing electrical connectivity to components coupled to the conductive tracks, mounted on the same or different layers.
While electrical connectivity is provided, the use of vias as described above presents an indirect connection path. For example, the current most often travels laterally along the conductive tracks between components and vias. An indirect current path such as this may limit current capacity as well as have a restrictive impedance characteristic. Additionally, some vias may be disproportionally loaded with respect to other vias, having to carry a greater proportion of the circuit current.
Managing heat generated by the embedded components may also be problematic, as dielectric laminates used for PCB layers generally have poor thermal characteristics. Heat management of the components within the PCB layers is important for predictable circuit performance and to prolong the life of the components.